The present invention relates to semiconductor devices, including integrated circuit (xe2x80x9cICxe2x80x9d) devices. More particularly, it relates to a method for planarizing and/or patterning surfaces of semiconductor devices that contain silica dielectric coatings and particularly nanoporous silica dielectric coatings, as well as to semiconductor devices produced by these methods.
Processes used for the fabrication of semiconductor devices almost invariably produce surfaces which significantly deviate from a planar configuration. With the trend toward greater large scale integration, this problem is expected to increase. For instance, the production of integrated circuits typically requires multiple layers to be formed sequentially on a semiconductor substrate. Many of these layers are patterned by selective deposition or selective removal of particular regions of each such layer. It is well known that small deviations from the planar condition in underlying layers become more pronounced with the addition of multiple additional layers of semiconductor and circuit features. Non-planar substrate surfaces can cause many problems that adversely impact the yield of finished products. For example, variations in interlevel dielectric thickness can result in failure to open vias, poor adhesion to underlying materials, step coverage, undesirable bends or turns in conductive metal layers, as well as xe2x80x9cdepth-of-focusxe2x80x9d problems for optical lithography.
In order to effectively fabricate multiple layers of interconnects it has become necessary to globally planarize the surface of certain layers during the multi-step process. Planarizing smoothes or levels the topography of microelectronic device layers in order to properly pattern the increasingly complex integrated circuits. IC features produced using optical or other lithographic techniques require regional and global dielectric planarization where the lithographic depth of focus is extremely limited, i.e., at 0.35 xcexcm and below. As used herein, the term xe2x80x9clocal planarizationxe2x80x9d refers to a condition wherein the film is planar or flat over a distance of 0 to about 5 linear micrometers. xe2x80x9cRegional planarizationxe2x80x9d refers to a condition wherein the film is planar or flat over a distance of about 5 to about 50 linear micrometers. xe2x80x9cGlobal planarizationxe2x80x9d refers to a condition wherein the film is planar or flat over a distance of about 50 to about 1000 linear micrometers. Without sufficient regional and global planarization, the lack of depth of focus will manifest itself as a limited lithographic processing window.
In addition, as IC feature sizes approach 0.25 xcexcm and below, problems with interconnect RC delay, power consumption and signal cross-talk have become increasingly difficult to resolve. The integration of low dielectric constant materials for interlevel dielectric (ILD) and intermetal dielectric (IMD) applications, is helping to solve these problems. One type of such low dielectric constant materials are nanoporous films prepared from silica, i.e., silicon-based materials. When air, with a dielectric constant of 1, is introduced into a suitable silica material having a nanometer-scale pore structure, dielectric films with relatively low dielectric constants (xe2x80x9ckxe2x80x9d), e.g., 3.8 or less, can be prepared on substrates, such as silicon wafers, suitable for fabricating integrated circuits. Thus, it is now important for the fabrication of the latest types of semiconductor devices, including integrated circuits, to provide methods for planarizing surfaces coated with nanoporous silica dielectric films.
One previously employed method of planarization is the etch-back technique. In that process, a material, i.e., a planarizing material, is deposited on a surface in a manner adapted to form a surface relatively free of topography. If the device layer and the overlying material layer have approximately the same etch rate, etching proceeds through the planarizing material and into the device layer with the surface configuration of the planarizing layer being transferred to the device material surface. Although this technique has been adequate for some applications where a modest degree of planarity is required, present planarizing materials and present methods for depositing the planarizing material are often inadequate to furnish the necessary planar surface for demanding applications such as in submicron device fabrication.
The degree of planarization is defined as the difference between the depth of the topography on the device surface ht, and the vertical distance between a high point and a low point on the overlying material surface hd, divided by the depth of the topography on the device surface ht:             h      t        -          h      d            h    t  
The degree of planarization, in percent, is                     h        t            -              h        d                    h      t        xc3x97  100
Generally, for typical device configurations, planarization using the etch-back technique has not been better than approximately 55% as calculated by the method described above for features greater than 300 microns in width. The low degree planarization achieved by this technique is attributed to a lack of planarity in the planarizing material. Thus, for elongated gap-type features greater than 300 microns in width and 0.5 microns in depth, the usefulness of an etch-back technique has been limited.
U.S. Pat. No. 5,736,424, incorporated herein by reference in its entirety, describes a method for planarizing surfaces of substrates, such as semiconductor materials, by adding a pressing step to an etch-back process. In this reference, an optically flat surface is impressed on a curable viscous polymer coating on the substrate surface in need of planarization, followed by polymerization of the coating. The polymer is selected to etch at the same rate as the surface in need of planarization, and the polymer coating is etched down to the substrate, which is planarized by the process. While an improved planarization is claimed, apparently by starting the etch-back with a flatter surface, an added process step and complexity is required. In addition, this reference fails to provide a solution for planarizing substrates coated with nanoporous dielectric films, since by their nature, such low density films cannot be etched at the same rate as the underlying substrate.
Chemical mechanical polishing (CMP) is another known method that has been effectively used in the art to globally planarize the entire surface of dielectric layers. According to this method, a grainy chemical composition or slurry is applied to a polishing pad and is used to polish a surface until a desired degree of planarity is achieved. CMP can rapidly remove elevated topographical features without significantly thinning flat areas. However, CMP does require a high degree of process control to obtain the desired results.
Dielectric films formed of organic polymers, such as polyarylene ether and/or fluorinated polyarylene ether polymers, have been planarized by applying CMP to a partially cured film, followed by a final curing, as described in co-owned U.S. application Ser. No. 09/023,415, filed on Feb. 13, 1998, the disclosure of which is incorporated by reference herein in its entirety. However, this reference fails to disclose how to planarize a silicon-based nanoporous dielectric material on the surface of a substrate.
For all of these reasons, there remains a need in the art for improved methods for achieving the planarization of substrates bearing nanoporous silica dielectric type materials.
In order to solve the above mentioned problems and to provide other improvements, the invention provides novel methods for effectively producing planarized nanoporous silica dielectric films with a low dielectric constant (xe2x80x9ckxe2x80x9d), e., typically ranging from about 1.5 to about 3.8, and compositions produced by these methods, having surfaces that do not deviate from a planar topography by more than 0.35xcexc, and having a degree of planarization of at least 55%, or greater.
Nanoporous silica films can be fabricated by using a mixture of a solvent composition and a silicon-based dielectric precursor, e.g., a liquid material suitable for use as a spin-on-glass (xe2x80x9cSOGxe2x80x9d) material, which is deposited onto a wafer by conventional methods of spin-coating, dip-coating, etc., and/or by chemical vapor deposition and related methods, as mentioned in detail above. The silica precursor is polymerized by chemical and/or thermal methods until it forms a gel. Further processing by solvent exchange, heating, electron beam, ion beam, ultraviolet radiation, ionizing radiation and/or other similar methods that result in curing and hardening of the applied film.
At an appropriate point in the process, the applied film is contacted with a planarization object, e., an object with a flat surface, or other type of surface suitable for the purpose. The planarization object and film are brought together with a force sufficient to effectively flatten the surface of the film, and thereafter the planarization object is separated from contact with the dielectric film, and any remaining process steps are conducted to produce a hardened nanoporous dielectric silica film.
Thus, the processes and compositions of the invention provide a substantially planarized nanoporous dielectric silica coating on a substrate formed by a process that includes: applying a composition that comprises a silicon-based precursor onto a substrate to form a coating on said substrate, and conducting the following steps:
(a) gelling or aging the applied coating,
(b) contacting the coating with a planarization object with sufficient pressure to transfer an impression of the object to the coating without substantially impairing formation of desired nanometer-scale pore structure,
(c) separating the planarized coating from the planarization object,
(d) curing said planarized coating;
wherein steps (a)-(d) are conducted in a sequence selected from the group consisting of
(a), (b), (c) and (d);
(a), (d), (b) and (c);
(b), (a), (d) and (c);
(b), (a), (c) and (d); and
(b), (c), (a) and (d);
The processes and compositions of the invention also provide a nanoporous dielectric silica coating on a substrate with a pattern impressed thereon by a process that includes: coating a substrate with a composition including a precursor for forming a nanoporous dielectric film, contacting the coating with a desired patterned surface with a pressure and for a time period sufficient in impress the pattern on said coating, and then separating the patterned surface from the coating. Optionally, the coating is aged or gelled before, during or after being contacted with the patterned surface, and, as noted above, the patterned surface can also be planar, or include multiple planar regions and/or other desirable features. The treated film can also be cured before, during or after pressing, using heat or any other art-known curing methods. If the curing is accomplished by heating, the heating can be applied by any art-standard devices, including a hot plate, a furnace, and even within the press, by applying heat to the film. Simply by way of example, for curing in a furnace, the heat can be applied at a temperature ranging from about 350xc2x0 C. to about 600xc2x0 C. for a time period ranging from about 30 sec to about 5 minutes.
In a further optional feature, the coating to be impressed with one or more planar surfaces and/or other useful topography and can include dielectric coatings, e.g., silicon-based dielectric coatings, which are not nanoporous. Thus, dielectric coatings on a substrate that are not foamed or porous can also optionally be planarized or impressed by the methods described herein.
Processes for producing the above-described nanoporous dielectric silica films, as well as integrated circuit devices incorporating these improved films, are also provided.